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| Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET DESCRIPTION Monolithic temperature and overload protected logic level power MOSFET in TOPFET2 technology assembled in a 3 pin surface mount plastic package. PIP3103-T QUICK REFERENCE DATA SYMBOL VDS ID PD Tj RDS(ON) PARAMETER Continuous drain source voltage Continuous drain current Total power dissipation Continuous junction temperature Drain-source on-state resistance MAX. 50 0.7 1.8 150 200 UNIT V A W C m APPLICATIONS General purpose switch for driving lamps motors solenoids heaters FEATURES TrenchMOS output stage Current limiting Overload protection Overtemperature protection Protection latched reset by input 5 V logic compatible input level Control of output stage and supply of overload protection circuits derived from input Low operating input current permits direct drive by micro-controller ESD protection on all pins Overvoltage clamping for turn off of inductive loads FUNCTIONAL BLOCK DIAGRAM DRAIN O/V CLAMP INPUT RIG POWER MOSFET LOGIC AND PROTECTION SOURCE Fig.1. Elements of the TOPFET. PINNING - SOT223 PIN 1 2 3 4 input drain source drain (tab) DESCRIPTION PIN CONFIGURATION 4 SYMBOL D TOPFET I P 1 2 3 S June 2001 1 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS ID II IIRM PD Tstg Tj PARAMETER Continuous drain source voltage Continuous drain current2 Continuous input current Non-repetitive peak input current Total power dissipation Storage temperature Continuous junction temperature 1 PIP3103-T CONDITIONS clamping tp 1 ms Ta = 25C normal operation3 MIN. -55 - MAX. 50 self limiting 3 10 1.8 150 150 UNIT V A mA mA W C C ESD LIMITING VALUE SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage CONDITIONS Human body model; C = 250 pF; R = 1.5 k MIN. MAX. 2 UNIT kV OVERVOLTAGE CLAMPING LIMITING VALUES At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL EDSM EDRM PARAMETER Non-repetitive clamping energy Repetitive clamping energy CONDITIONS Ta 25C; IDM < ID(lim); inductive load Tsp 125C; IDM = 50 mA; f = 250 Hz MIN. MAX. 100 5 UNIT mJ mJ OVERLOAD PROTECTION LIMITING VALUES With the protection supply provided via the input pin, TOPFET can protect itself from short circuit loads. Overload protection operates by means of drain current limiting and activating the overtemperature protection. SYMBOL VDDP PARAMETER REQUIRED CONDITION MIN. MAX. 35 UNIT V Protected drain source supply voltage VIS 4 V THERMAL CHARACTERISTICS SYMBOL Rth j-sp Rth j-b Rth j-a PARAMETER Thermal resistance Junction to solder point Junction to board4 Junction to ambient CONDITIONS MIN. TYP. 12 40 MAX. 18 70 UNIT K/W K/W K/W Mounted on any PCB Mounted on PCB of fig. 22 1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy. 2 Refer to OVERLOAD PROTECTION CHARACTERISTICS. 3 Not in an overload condition with drain current limiting. 4 Temperature measured 1.3 mm from tab. June 2001 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET OUTPUT CHARACTERISTICS Limits are for -40C Tmb 150C; typicals are for Tmb = 25 C unless otherwise specified SYMBOL PARAMETER Off-state V(CL)DSS IDSS Drain-source clamping voltage CONDITIONS VIS = 0 V ID = 10 mA ID = 200 mA; tp 300 s; 0.01 Drain source leakage current On-state RDS(ON) Drain-source resistance VDS = 40 V Tmb = 25 C VIS 4 V; tp 300 s; 0.01 ID = 100 mA Tmb = 25 C 150 50 50 60 0.1 MIN. TYP. PIP3103-T MAX. UNIT 70 100 10 V V A A 380 200 m m INPUT CHARACTERISTICS The supply for the logic and overload protection is taken from the input. Limits are for -40C Tmb 150C; typicals are for Tmb = 25C unless otherwise specified SYMBOL VIS(TO) IIS IISL VISR tlr V(CL)IS RIG PARAMETER Input threshold voltage Input supply current Input supply current Protection reset voltage1 Latch reset time Input clamping voltage Input series resistance2 to gate of power MOSFET CONDITIONS VDS = 5 V; ID = 1 mA Tmb = 25C normal operation; protection latched; reset time tr 100 s VIS1 = 5 V, VIS2 < 1 V II = 1.5 mA Tmb = 25C VIS = 5 V VIS = 4 V VIS = 5 V VIS = 3 V MIN. 0.6 1.1 100 80 200 130 1.5 10 5.5 TYP. 1.6 220 195 400 250 2 40 33 MAX. 2.4 2.1 400 330 650 430 2.9 100 8.5 UNIT V V A A A A V s V k 1 The input voltage below which the overload protection circuits will be reset. 2 Not directly measureable from device terminals. June 2001 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET OVERLOAD PROTECTION CHARACTERISTICS TOPFET switches off to protect itself when one of the overload thresholds is exceeded. It remains latched off until reset by the input. SYMBOL ID PARAMETER Overload protection Drain current limiting CONDITIONS -40C Tj 150C VIS = 5 V VIS = 4.5 V VIS = 4 V to 5.5 V VIS = 5 V for protection to operate which determines trip time1 from ID 280 mA or VDS 100 mV 150 165 17 1.6 0.8 0.7 0.6 1.3 MIN. TYP. PIP3103-T MAX. 1.7 1.8 UNIT A A A Short circuit load protection PD(TO) TDSC Tj(TO) Overload power threshold Characteristic time Overtemperature protection - W ms C Threshold junction temperature VIS = 4 V to 5.5 V SWITCHING CHARACTERISTICS Ta = 25C; resistive load RL = 50 ; adjust VDD to obtain ID = 250 mA; refer to test circuit and waveforms SYMBOL td on tr td off tf PARAMETER Turn-on delay time Rise time Turn-off delay time Fall time VIS: 5 V 0 V CONDITIONS VIS: 0 V 5 V MIN. TYP. 5 11 25 14 MAX. 12 30 65 35 UNIT s s s s REVERSE DIODE LIMITING VALUE SYMBOL IS PARAMETER Continuous forward current CONDITIONS Tmb 25 C; VIS = 0 V MIN. MAX. 2 UNIT A REVERSE DIODE CHARACTERISTICS Limits are for -40C Tmb 150C; typicals are for Tmb = 25C unless otherwise specified SYMBOL VSDO trr PARAMETER Forward voltage Reverse recovery time CONDITIONS IS = 2 A; VIS = 0 V; tp = 300 s not applicable2 MIN. TYP. 0.83 MAX. 1.1 UNIT V - 1 Trip time td sc varies with overload dissipation PD according to the formula td sc TDSC / [ PD / PD(TO) - 1 ]. 2 The reverse diode of this type is not intended for applications requiring fast reverse recovery. June 2001 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET PIP3103-T Normalised Power Derating, PD (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 2 a Normalised RDS(ON) = f(Tj) 1.5 1 0.5 0 -50 0 50 Tj / C 100 150 Fig.2. Normalised limiting power dissipation. PD% = 100PD/PD(25C) = f(Tmb) ID / A CURRENT LIMITING OCCURS WITHIN SHADED REGION Fig.5. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25C = f(Tj); ID = 100 mA; VIS = 4.4 V RDS(ON) / mOhm 2.0 350 300 1.5 TYP. 250 200 MAX. 1.0 150 100 TYP. 0.5 50 0 0 0 20 40 60 80 Tamb / C 100 120 140 0 1 2 3 4 VIS / V 5 6 7 8 Fig.3. Continuous drain current. ID = f(Tamb); condition: VIS = 5 V ID / A Fig.6. Typical on-state resistance, Tj = 25C. RDS(ON) = f(VIS); conditions: ID = 100 mA, tp = 300 s 2 2 ID / A 1.5 VIS / V = 7 6 5 4 1.5 1 1 0.5 0.5 0 0 4 8 12 16 VDS / V 20 24 28 32 0 0 1 2 3 VIS / V 4 5 6 7 Fig.4. Typical on-state characteristics, Tj = 25C. ID = f(VDS); parameter VIS; tp = 300 s Fig.7. Typical transfer characteristics, Tj = 25C. ID = f(VIS); conditions: VDS = 10 V, tp = 300 s June 2001 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET PIP3103-T 200 195 190 185 180 175 170 165 160 Tj(TO) / C 4 VIS(TO) / V DATA BELOW 4V IS FOR INFORMATION ONLY. ALL SPEC. VALUES ARE FOR NORMAL OPERATION AT 4V AND ABOVE. 3 MAX. 2 TYP. 1 MIN. 2 3 4 5 VIS / V 6 7 8 0 -50 0 50 Tj / C 100 150 Fig.8. Typical overtemperature protection threshold. Tj(TO) = f(VIS) Ii / mA Fig.11. Input threshold voltage. VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V II / mA 1 10 9 8 7 6 0.5 Iisl 5 4 3 Iis 0 2 1 0 1 2 3 4 Vis / V 5 6 7 8 0 0 2 4 VIS / V 6 8 10 Fig.9. Typical DC input characteristics, Tj = 25C. IIS & IISL = f(VIS); normal operation & protection latched Fig.12. Typical input clamping characteristic. II = f(VIS); normal operation, Tj = 25C. 500 IIS & IISL / uA 5V 1600 1400 1200 1000 3V 1s / tdsc 400 VIS / V = 300 5V 4V 100 = IIS = IISL 0 -50 0 50 Tj / C 100 150 800 600 400 200 0 0 5 10 15 20 25 Pd / W 30 35 40 45 50 200 Fig.10. Typical DC input currents. IIS & IISL = f(Tj); parameter VIS; normal & latched Fig.13. Typical overload protection response time. 1 / tdsc = f(PD); VIS 4 V, Tj 125C. June 2001 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET PIP3103-T 3 2.8 2.6 2.4 2.2 2 1.8 VISR / V 15 VIS & VDS / V VDS 10 VIS 5 1.6 1.4 1.2 1 -50 0 -25 0 25 50 Tj / C 75 100 125 150 -40 -20 0 20 40 60 80 time / us 100 120 140 160 Fig.14. Typical Protection reset voltage. VISR = f(Tj); tlr = 100 s. ID / mA Fig.17. Typical switching waveforms, resistive load . RL = 50 ; adjust VDD to obtain ID = 250 mA; Tj = 25C IDSS 400 10 uA 300 1 uA 200 TYP. 100 nA 100 0 56 58 60 62 VDS / V 64 66 68 10 nA -50 0 50 Tj / C 100 150 Fig.15. Overvoltage clamping characteristic, 25C. ID = f(VDS); conditions: VIS = 0 V; tp 300 s Fig.18. Typical drain source leakage current IDSS = f(Tj); conditions: VDS = 40 V; VIS = 0 V. VDD RL VDS TOPFET I P D measure D.U.T. S 0V VIS Fig.16. Test circuit for resistive load switching times. VIS = 5 V June 2001 7 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET PIP3103-T 1E+02 Zth j-amb / (K / W) D= 0.5 0.2 0.1 0.05 0.02 1E+01 1 P D 1E-01 0 1E-02 1E-07 1E-05 1E-03 t/s 1E-01 tp D= tp T t 1E+03 T 1E+01 Fig.19. Transient thermal impedance, mounted on SOT223 PCB. Zth j-a = f(t); parameter D = tp / T June 2001 8 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET MECHANICAL DATA Plastic surface mounted package; collector pad for good heat transfer; 4 leads PIP3103-T SOT223 D B E A X c y HE b1 vMA 4 Q A A1 1 e1 e 2 bp 3 wM B detail X Lp 0 2 scale 4 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.8 1.5 A1 0.10 0.01 bp 0.80 0.60 b1 3.1 2.9 c 0.32 0.22 D 6.7 6.3 E 3.7 3.3 e 4.6 e1 2.3 HE 7.3 6.7 Lp 1.1 0.7 Q 0.95 0.85 v 0.2 w 0.1 y 0.1 OUTLINE VERSION SOT223 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 96-11-11 97-02-28 Fig.20. SOT223 surface mounting package3. 3 For further information, refer to surface mounting instructions for SOT223 envelope. Epoxy meets UL94 V0 at 1/8". Net Mass: 0.11 g June 2001 9 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET MOUNTING INSTRUCTIONS Dimensions in mm. 3.8 min PIP3103-T PRINTED CIRCUIT BOARD Dimensions in mm. 36 1.5 min 18 60 9 2.3 1.5 min (3x) 6.3 4.6 4.5 10 1.5 min 4.6 7 15 50 Fig.21. Soldering pattern for surface mounting. Fig.22. PCB for thermal resistance and power rating. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 m thick). June 2001 10 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET PIP3103-T DEFINITIONS DATA SHEET STATUS DATA SHEET STATUS4 Objective data PRODUCT STATUS5 Development DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in ordere to improve the design and supply the best possible product This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A Preliminary data Qualification Product data Production Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 2001 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 4 Please consult the most recently issued datasheet before initiating or completing a design. 5 The product status of the device(s) described in this datasheet may have changed since this datasheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. June 2001 11 Rev 1.000 |
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